The present invention relates to a semiconductor memory device, and more particularly to a cell array for storing data and a bit line sense amplifier (BLSA) for sensing data by amplifying voltages loaded at a bit line pair.
FIG. 1 is a block diagram of a conventional semiconductor memory device having a shared BLSA structure. The semiconductor memory device having the shared BLSA structure provides a BLSA shared by a plurality of cell arrays. A BLSA of the semiconductor memory device shown in FIG. 1 is shared by two cell arrays.
As shown, the semiconductor memory device includes a plurality of block selection units, a plurality of bit line equalization signal (BLEQ) generation units, a plurality of cell arrays, and a plurality of BLSA units. A block selection unit, e.g., BLOCK SELECTION UNIT 0, selects a corresponding cell array of the semiconductor memory device to/from which the data is input/output. A BLEQ generation unit, e.g., BLEQ GENERATION UINT 0, generates a bit line equalization signal, e.g., BLEQ 0, for initializing a bit line pair by equalizing voltages loaded at the bit line pair. A cell array, e.g., CELL ARRAY 0, stores the data. A BLSA unit, e.g., BLSA 0, senses voltage differences between the voltages loaded at the bit line pair.
FIG. 2 is a detailed diagram of two cell arrays and a BLSA depicted in FIG. 1.
The second BLSA unit BLSA 1 is shared by the two cell arrays CELL ARRAY 0 and CELL ARRAY 1. The second BLSA unit BLSA 1 includes a BLSA 201, two bit line equalizers 202U and 202D, a precharger 203, two isolators 204U and 204D, and an output unit 205. The BLSA 201 amplifies a voltage difference between voltages loaded at a bit line pair, e.g., BLU and BLBU. A bit line equalizer, e.g., 202U, equalizes the voltages loaded at the bit line pair, e.g., the upper bit line pair BLU and BLBU, in response to the bit line equalization signal BLEQ. The precharger 203 precharges the bit line pairs at a precharge voltage VBLP in response to the bit line equalization signal BLEQ. The isolators 204U and 204B isolate the cell array units CELL ARRAY 0 and CELL ARRAY 1 and the BLSA 201. In detail, the first isolator 204U isolates the first cell array CELL ARRAY 0 and the BLSA 201; and the second isolator 204D isolates the second cell array CELL ARRAY 1 and the BLSA 201. The output unit 205 outputs the data loaded at the bit line pair to the output line SIO and SIOB in response to an output signal YI, which is generated based on a column address.
The block selection unit shown in FIG. 1 selects a corresponding cell array in response to an active command. In case that the first cell array CELL ARRAY 0 is required to be selected, the first block selection unit BLOCK SELECTION UNIT 0 outputs a first block selection signal bs_0. In response to the first block selection signal bs_0, the first and the second BLEQ generation units BLEQ GENERATION UNIT 0 and BLEQ GENERATION UNIT 1 respectively disable the first and the second BLEQ signals BLEQ0 and BLEQ1 to a logic low level. Accordingly, the first and the second BLSA units BLSA 0 and BLSA 1 neighboring the first cell array CELL ARRAY 0 no longer equalize their respective bit line pairs. That is, the NMOS transistors M0 to M3, which receive the BLEQ signal, are turned off. Meanwhile, the other block selection signals, e.g., bs_1, are enabled at a logic high level and, therefore, the bit line pairs included in unselected cell arrays, e.g., CELL ARRAY 1, are equalized. After a precharge command is activated, the BLEQ signal BLEQ becomes a logic high level. Thereafter, the bit line pair of the first cell array CELL ARRAY 0 is precharged with the precharge voltage VBLP.
As mentioned above, when the first cell array CELL ARRAY 0 is selected in response to the active command, the bit line equalizers included in the first and the second BLSA units BLSA0 and BLSA1 do not perform an equalization operation. Herein, the down bit line pair BLD and BLBD included in the second cell array CELL ARRAY 1 and connected to the second BLSA unit BLSA 1 is disconnected with the second BLSA unit BLSA 1 by the second isolator 204D. The down bit line pair BLD and BLBD is disconnected during an active operation. When the first cell array CELL ARRAY 0 starts to perform the active operation in response to the active command, the down bit line pair BLD and BLBD are precharged with the precharge voltage VBLP. While the first cell array CELL ARRAY 0 proceeds the active operation, a current leakage occurs in the down bit line pair BLD and BLBD and, therefore, voltage levels loaded at the down bit line pair BLD and BLBD are lowered. In this case, when the second BLSA unit BLSA 1 starts a precharge operation, a precharge time increases because the voltage level loaded at the down bit line pair BLD and BLBD has been lowered. Further, in a memory device with large capacity, the size of the cell array is much larger than that of the BLSA unit. Accordingly, a conventional method for equalizing the bit line pair, arranged both in the BLSA unit and the cell array, by only using the bit line equalizer included in the BLSA unit spends long time and, therefore, is inefficient.